I would like to have a working Arduino Uno code to generate 20kHz PWM signal with variable duty cycle.
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ATmega328P 8-bit AVR Microcontroller with 32K Bytes In-System Programmable Flash DATASHEET Features ● High performance, low power AVR® 8-bit microcontroller ● Advanced RISC architecture ● ● ● ● ● 131 powerful instructions – most single clock cycle execution 32 8 general purpose working registers Fully static operation Up to 16MIPS throughput at 16MHz On-chip 2-cycle multiplier ● High endurance non-volatile memory segments ● ● ● ● ● 32K bytes of in-system self-programmable flash program memory 1Kbytes EEPROM 2Kbytes internal SRAM Write/erase cycles: 10,000 flash/100,000 EEPROM Optional boot code section with independent lock bits ● In-system programming by on-chip boot program ● True read-while-write operation ● Programming lock for software security ● Peripheral features ● Two 8-bit Timer/Counters with separate prescaler and compare mode ● One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode ● Real time counter with separate oscillator ● Six PWM channels ● 8-channel 10-bit ADC in TQFP and QFN/MLF package ● Temperature measurement ● Programmable serial USART ● Master/slave SPI serial interface ● Byte-oriented 2-wire serial interface (Phillips I2C compatible) ● Programmable watchdog timer with separate on-chip oscillator ● On-chip analog comparator ● Interrupt and wake-up on pin change ● Special microcontroller features ● ● ● ● Power-on reset and programmable brown-out detection Internal calibrated oscillator External and internal interrupt sources Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby, and extended standby 7810D-AVR-01/15 ● I/O and packages ● 23 programmable I/O lines ● 32-lead TQFP, and 32-pad QFN/MLF ● Operating voltage: ● 2.7V to 5.5V for ATmega328P ● Temperature range: ● Automotive temperature range: –40°C to +125°C ● Speed grade: ● 0 to 8MHz at 2.7 to 5.5V (automotive temperature range: –40°C to +125°C) ● 0 to 16MHz at 4.5 to 5.5V (automotive temperature range: –40°C to +125°C) ● Low power consumption ● Active mode: 1.5mA at 3V – 4MHz ● Power-down mode: 1µA at 3V 2 ATmega328P [DATASHEET] 7810D–AVR–01/15 Pin Configurations Figure 1-1. Pinout PC2 (ADC2/PCINT10) PC3 (ADC3/PCINT11) PC4 (ADC4/SDA/PCINT12) PC5 (ADC5/SCL/PCINT13) PC6 (RESET/PCINT14) PD0 (RXD/PCINT16) PD1 (TXD/PCINT17) PD2 (INT0/PCINT18) TQFP Top View 32 31 30 29 28 27 26 25 (PCINT19/OC2B/INT1) PD3 1 24 PC1 (ADC1/PCINT9) (PCINT20/XCK/T0) PD4 2 23 PC0 (ADC0/PCINT8) GND 3 22 ADC7 VCC 4 21 GND GND 5 20 AREF VCC 6 19 ADC6 (PCINT6/XTAL1/TOSC1) PB6 7 18 AVCC (PCINT7/XTAL2/TOSC2) PB7 8 17 PB5 (SCK/PCINT5) (PCINT4/MISO) PB4 PC2 (ADC2/PCINT10) PC3 (ADC3/PCINT11) PC4 (ADC4/SDA/PCINT12) PC5 (ADC5/SCL/PCINT13) PC6 (RESET/PCINT14) PD0 (RXD/PCINT16) PD1 (TXD/PCINT17) 32 MLF Top View PD2 (INT0/PCINT18) (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT1/OC1A) PB1 (PCINT0/CLKO/ICP1) PB0 (PCINT23/AIN1) PD7 10 11 12 13 14 15 16 (PCINT22/OC0A/AIN0) PD6 9 (PCINT21/OC0B/T1) PD5 32 31 30 29 28 27 26 25 (PCINT19/OC2B/INT1) PD3 1 24 PC1 (ADC1/PCINT9) (PCINT20/XCK/T0) PD4 2 23 PC0 (ADC0/PCINT8) GND 3 22 ADC7 VCC 4 21 GND GND 5 20 AREF VCC 6 19 ADC6 (PCINT6/XTAL1/TOSC1) PB6 7 18 AVCC (PCINT7/XTAL2/TOSC2) PB7 8 17 PB5 (SCK/PCINT5) (PCINT4/MISO) PB4 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT1/OC1A) PB1 (PCINT0/CLKO/ICP1) PB0 (PCINT23/AIN1) PD7 NOTE: Bottom pad should be soldered to ground. 10 11 12 13 14 15 16 (PCINT22/OC0A/AIN0) PD6 9 (PCINT21/OC0B/T1) PD5 1. ATmega328P [DATASHEET] 7810D–AVR–01/15 3 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator amplifier. If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of port B are elaborated in Section 13.3.1 “Alternate Functions of Port B” on page 65 and Section 8. “System Clock and Clock Options” on page 24. 1.1.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 PC6/RESET If the RSTDISBL fuse is programmed, PC6 is used as an input pin. If the RSTDISBL fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page 261. Shorter pulses are not guaranteed to generate a reset. The various special features of port C are elaborated in Section 13.3.2 “Alternate Functions of Port C” on page 68. 1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port D pins that are externally pulled low will source current if the pull-up resistors are activated. The port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of port D are elaborated in Section 13.3.3 “Alternate Functions of Port D” on page 70. 1.1.7 AVCC AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC. 1.1.8 AREF AREF is the analog reference pin for the A/D converter. 4 ATmega328P [DATASHEET] 7810D–AVR–01/15 1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 1.2 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of actual ATmega328P AVR® microcontrollers manufactured on the typical process technology. automotive min and max values are based on characterization of actual ATmega328P AVR microcontrollers manufactured on the whole process excursion (corner run). 1.3 Automotive Quality Grade The ATmega328P have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the ATmega328P have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only one temperature. Table 1-1. Temperature Grade Identification for Automotive Products Temperature Temperature Identifier Comments –40°C; +125°C Z Full automotive temperature range ATmega328P [DATASHEET] 7810D–AVR–01/15 5 2. Overview The Atmel® ATmega328P is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328P achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram GND Watchdog Timer Watchdog Oscillator Oscillator Circuits/ Clock Generation VCC Power Supervision POR/ BOD and RESET debugWIRE Flash SRAM Program Logic AVR CPU EEPROM AVCC AREF DATA BUS GND 8-bit T/C 0 16-bit T/C 1 A/D Conv. 8-bit T/C 2 Analog Comp. Internal Bandgap USART 0 SPI TWI PORT D (8) PORT B (8) PORT C (7) 2 6 RESET XTAL[1..2] PD[0..7] 6 ATmega328P [DATASHEET] 7810D–AVR–01/15 PB[0..7] PC[0..6] ADC[6..7] The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel® ATmega328P provides the following features: 32K bytes of in-system programmable flash with read-while-write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byteoriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable watchdog timer with internal oscillator, and five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire serial interface, SPI port, and interrupt system to continue functioning. The power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC noise reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel high density non-volatile memory technology. The on-chip ISP flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the application flash memory. Software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system self-programmable flash on a monolithic chip, the Atmel ATmega328P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega328P AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ATmega328P [DATASHEET] 7810D–AVR–01/15 7 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Data Retention Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 8 ATmega328P [DATASHEET] 7810D–AVR–01/15 6. AVR CPU Core 6.1 Overview This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 6-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registers Control Lines Indirect Addressing Instruction Decoder Direct Addressing Instruction Register ALU Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory. ATmega328P [DATASHEET] 7810D–AVR–01/15 9 The fast-access register file contains 32 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR® instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program flash memory space is divided in two sections, the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that writes into the application flash memory section must reside in the boot program section. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 – 0x5F. In addition, the ATmega328P has extended I/O space from 0x60 – 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 6.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Section “” on page 281 for a detailed description. 6.3 Status Register The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 10 ATmega328P [DATASHEET] 7810D–AVR–01/15 6.3.1 SREG – AVR Status Register The AVR status register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The bit copy instructions BLD (bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
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